As seen in FIG. 1, during a conventional flip-chip attach process, a microelectronic die 10 including conductive bumps 12 thereon, such as copper bumps, for example, is brought into registration with solder bumps 14 on a package substrate 16 having corresponding bumping sites (or surface finish layers) 18 supporting the solder bumps and an optional solder resist layer 19 supported on a substrate panel 15. Typically to move and position and the die and the substrate relative to one another during flip chip attachment, a pick and place tool is used. A pick-and-place tool, as is well known, may include a conveyer system including a rail 5 to move the substrate into and out of a die alignment position, a bond head 21 to move the die into alignment with the substrate a vision system (not shown), etc. After die 10 has been placed onto the substrate 16, the die-substrate combination is typically moved by rail 5 to go to the next process step. When the combination departs from the area of the bond head 21 the combination is subjected to acceleration forces and when the rail stops at the next toot, the combination is subjected to deceleration forces. Such acceleration and deceleration can cause movement of the die with respect to the substrate. The above problem is exacerbated in the case of a large die, such as one having a size above about 10×10 mm, where the inertia of the die is larger for the same acceleration or deceleration. Referring still to FIG. 1, typically, the solder bumps 14 are fluxed with flux 20. The flux serves to remove any residual oxide on the solder bumps prior to die attach. Even though the tackiness of the flux 20 can help to hold the die 10 in place during movement of the rail 5, such tackiness is sometimes not strong enough to counteract the acceleration/deceleration mentioned above.
Prior art copper bumps are known which show dimples on a surface thereof adapted to receive the solder bumps thereon. An example of a dimpled bump is provided in FIG. 2 which, except for the dimple on the die bump, has components identical to those of FIG. 1. As seen in FIG. 2, a small dimple 23 is defined in bump 12. Such dimples are usually brought about as a result of an un-optimized plating process involving the formation of the die bumps. A typical diameter of the dimple is about 10 μm or less, and a typical depth about several micrometers on a die bump having a diameter of about 105 μm and a height of about 47 μm. After placement of die 10 onto substrate 16, flux 20 provided on the solder bumps 14 of the substrate 16 may get trapped in the dimple 23 due to surface tension of the flux, and also as a result of a plugging effect of the solder bumps 14. Flux entrapment as described above, however, may lead to voids within solder joints formed to bond the die to the substrate, in this way resulting in poor yield and/or poor performance of the die-substrate package. The entrapped flux reduces the mechanical and electrical integrity of the joints to be formed between the die and the substrate. Entrapped flux in a solder joint reduces the mechanical stress level that can be sustained by the joint, and also reduces the area of current path, in this way resulting in a reduced current carrying capability of the joint. Another disadvantage of having a solder void induced by flux entrapment is a current crowding effect around the void which would accelerate electromigration and possibly lead to early failure of the joint.
The prior art fails to provide a reliable solution for the misalignment of microelectronic dies with respect to package substrate.
For simplicity and clarity of illustration, elements in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Where considered appropriate, reference numerals have been repeated among the drawings to indicate corresponding or analogous elements.